Elbrus-2S+

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Elbrus-2S+
Elbrus-2C+.jpg
Produced 2011
Designed by MCST
Common manufacturer(s)
Max. CPU clock rate 300 MHz to 800 MHz
Instruction set Elbrus 2000, x86
Cores 6

Elbrus-2S+ (Russian: Эльбрус-2С+) is a multi-core microprocessor based on the Elbrus 2000 architecture developed by Moscow Center of SPARC Technologies (MCST) [2][3][4] There are multiple reports regarding the evolution of this technology for the purpose of import substitution in Russia, which was raised by several ministries on July, 2014 due to economic sanctions in response to 2014 pro-Russian unrest in Ukraine.[5][6][7][8] In December 2014, it was announced that Mikron start pilot production of a dual-core variant of this microprocessor called Elbrus-2SM (Russian: Эльбрус-2СM) using a 90 nanometer CMOS manufacturing process in Zelenograd, Russia.[1][9][10][11][12]

Technology

The Elbrus-4S CPU is reported to have built in support for Intel x86 emulation as well as a native VLIW mode where it can perform up to 23 instructions per clock cycle.[13][14][15] When programs are built for Elbrus 2000 native mode, the compiler determines how the different operations shall be distributed over the 23 computing units before saving the final program. This means that no dynamic scheduling is needed during runtime, thus reducing the amount of work the CPU has to perform every time program in executed. Because static scheduling only needs to be performed one time when the program is built, more advanced algorithms for finding the optimal distribution of work can be employed.[16][17]

Specifications

Elbrus-2S+[18] Elbrus-2SМ[19] Elbrus-4S[20]
Produced 2011 2014 2014
Process CMOS 90 nm CMOS 90 nm CMOS 65 nm
Clock rate 500 MHz 300 MHz 800 MHz
Elbrus 2000 CPU cores

Elcore-09 DSP cores

2

4

2

0

4

0

Peak performance (CPU + DSP)
  • 64-bit
  • 64-bit
  • 32-bit
  • 32-bit
  • 16-bit

20 + 2 GIPS
8 + 0 GFlops
33 + 16 GIPS
16 + 12 GFlops
43 + 48 GIPS


12 GIPS
4.8 GFlops
19.8 GIPS
9.6 GFlops
 



25 GFlops
107 GIPS
50 GFlops
 

L1 instruction cache (per core) 64 KB 64 KB 128 KB
L1 data cache (per core) 64 KB 64 KB 64 KB
L2 cache (per core) 1 MB 1 MB 8 MB
DSP cache (per DSP core) 128 KB
Data transfer rate to cache 16 GByte/s
Data transfer rate to main memory 12.8 GByte/s 38.4 GByte/s
Communications
  • number of channels for interprocessor communications
  • channel bandwidth for interprocessor communications
  • number of input-output channels
  • channel bandwidth for input-output

3
4 GByte/s
2
2 GByte/s


3
12 GByte/s
1
4 GByte/s

Crystal area 289 sq. mm 380 sq. mm
Transistors 368 million >300 million [1] 986 million
Connection layers 9 9
Packing/pins HFCBGA/1296 HFCBGA/1600
Package size 37.5×37.5×2.5 mm 42.5×42.5×3.2 mm
Voltage 1.0/1.8/2.5 V 1.2/1.8/ 2.5 V 1.1/1.5/2.5/3.3 V
Power consumption ~25 W ~45 W
Producer TSMC Taiwan Mikron Russia [1] TSMC Taiwan

South Bridge

The south bridge for the Elbrus 2000 chipset, which connects peripherals and bus to the CPU is developed by MCST. It is also compatible with the MCST-R1000.[21][22]

KPI 1991VG1YA 1026A010
Produced 2010
Process CMOS 0.13 µm
Clock rate 250 MHz
serial bus for communication with the microprocessor 1 GByte/s - receiving, 1 GByte/s - transmission
PCI Express controller, revision 1.0a 8 lines
PCI controller, version 2.3 32/64-bits at clock frequencies of 33/66 MHz
Ethernet controller, 1 GByte/s 1 port
SATA 2.0 controller 4 ports
IDE controller, PATA-100 2 ports for 2 devices
USB 2.0 controller 2 ports
audio interface controller, AC-97 2-channel stereo
Serial controller, RS-232 and RS-485 2 ports
Parallel interface controller, IEEE-1284 with DMA support 1 port
Programmable universal input-output (GPIO) controller 16 signals
I²C interface Channel 4
SPI Interface Supports for 4 devices
Interrupt control subsystems 2 PIC + 1 IOAPIC
Timers System timer and watchdog timer.
Crystal area 112 sq. mm
Transistors 30 million
Packing/pins HFCBGA/1156
Package size 35×35×3.2 mm
Voltage 1.2/3.3V
Power consumption ~6 W

Applications

In December 2012, Kraftway announced that it will deliver an Elbrus based PC together with its partner MCST.[23][24][25]

On August, 2013 Kuyan, Gusev, Kozlov, Kaimuldenov and Kravtsunov from MCST has published an article based on their experience with building and deployment of Debian Linux for the Elbrus computer architecture. It was done using a hybrid compiler toolchain (cross and native), for Elbrus-2S+ and Intel Core 2 Duo.[26]

In December 2014, an implementation of the OpenGL 3.3 standard was demonstrated by running the game Doom 3 on an Elbrus-4S, clocked at 720 MHz, using a Radeon graphics card with 2 gigabytes of video memory.[27]

In April 2015, MCST announced two new products based on the Elbrus-4S CPU: One 19-inch rack server with four CPUs (16 cores) and one personal computer.[28]

In December 2015 the first shipment of PCs based on VLIW CPU Elbrus-4s was made in Russia [29]

See also

References

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  18. Specifications Elbrus-2C+
  19. Specifications Elbrus-2SM
  20. Specifications Elbrus-4C
  21. Lua error in package.lua at line 80: module 'strict' not found.
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  25. Lua error in package.lua at line 80: module 'strict' not found.
  26. Experience of Building and Deployment Debian on Elbrus Architecture, Date obtained from creation date of pdf file
  27. Lua error in package.lua at line 80: module 'strict' not found.
  28. Lua error in package.lua at line 80: module 'strict' not found.
  29. http://tass.ru/ekonomika/2498729

External links