File:4T SRAM Cell.png
From Infogalactic: the planetary knowledge core
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Summary
A schematic of a four-transistor SRAM cell. The resistors are typically implemented in a special high-resistivity polysilicon layer.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 03:12, 29 October 2021 | | 910 × 567 (20 KB) | Thales (talk | contribs) | |
| 16:05, 9 January 2017 | No thumbnail | (0 bytes) | 127.0.0.1 (talk) | A schematic of a four-transistor SRAM cell. The resistors are typically implemented in a special high-resistivity polysilicon layer. |
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