Infineon TriCore

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TriCore
Designer Infineon Technologies AG
Bits 32-bit
Introduced 1999
Version 2
Design RISC
Type Load-store
Endianness Little for data memory and CPU registers
Open No
Registers
16 AddrReg, 16 DataReg, PCXI, PSW, PC

TriCore is a 32-bit microcontroller architecture from Infineon. It unites the elements of a RISC processor core, a microcontroller and a DSP in one chip package.

History and background

In 1999, Infineon launched the first generation of AUDO (Automotive unified processor) which is based on what the company describes as a 32-bit ”unified RISC/MCU/DSP microcontroller core,” called TriCore, which is as of 2011 on its fourth generation, called AUDO MAX (version 1.6).

TriCore is a heterogeneous, asymmetric dual core architecture with a peripheral control processor that enables user modes and core system protection.

Infineon’s AUDO families[1] targets gasoline and diesel engine management systems, applications in hybrid and electric vehicles as well as transmission, active and passive safety and chassis applications. It also targets industrial applications, e.g. optimized motor control applications and signal processing.

Different models offer different combinations of memories, peripheral sets, frequencies, temperatures and packaging. Infineon also offers software claimed to help manufacturers meet SIL/ASIL[2] safety standards. All members of the AUDO family are binary-compatible and share the same development tools. An AUTOSAR library that enables existing code to be integrated is also available.

Safety

Infineon’s portfolio includes microcontrollers with additional hardware features as well as SafeTcore safety software and a watchdog IC.[3]

AUDO families cover safety applications including active suspension and driver assistant systems and also EPS and chassis domain control. Some features of the product portfolio are memory protection, redundant peripherals, MemCheck units with integrated CRCs, ECC on memories, integrated test and debug functionality and FlexRay.

References

External links

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