PIC instruction listings

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The PIC instruction set refers to the set of instructions that a Microchip Technology PIC or dsPIC microcontroller supports. The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup.

PICmicro chips have a Harvard architecture, and instruction words are unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.

Baseline core devices (12 bit)

The instruction set is as follows. Register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.

Models with more than 32 bytes of registers (special function registers plus RAM) support multiple banks of registers. There are two methods of doing this:

  1. Most use high high-order bits of the file select register to select the current register bank.
  2. Some more recent models have a separate 3-bit bank select register, and a MOVLB instruction to set it.
12-bit PIC instruction set
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Mnemonic C
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Z
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Description
0 0 0 0 0 0 0 opcode Miscellaneous instructions
0 0 0 0 0 0 0 0 0 0 0 0 NOP No operation (MOVW 0,W)
0 0 0 0 0 0 0 0 0 0 1 0 OPTION Copy W to OPTION register
0 0 0 0 0 0 0 0 0 0 1 1 SLEEP Go into standby mode
0 0 0 0 0 0 0 0 0 1 0 0 CLRWDT Restart watchdog timer
0 0 0 0 0 0 0 0 0 1 f TRIS f Copy W to tri-state register (f = 1, 2 or 3)
0 0 0 0 0 0 0 1 0 k MOVLB k* Set bank select register to k
0 0 0 0 0 0 0 1 1 1 1 0 RETURN Return from subroutine, W unmodified
0 0 0 0 0 0 0 1 1 1 1 1 RETFIE Return from interrupt; return & enable interrupts
0 0 opcode d register ALU operations: dest ← OP(f,W)
0 0 0 0 0 0 1 f MOVWF f dest ← W
0 0 0 0 0 1 d f CLR f,d Z dest ← 0, usually written CLRW or CLRF f
0 0 0 0 1 0 d f SUBWF f,d C Z dest ← f−W (dest ← f+~W+1)
0 0 0 0 1 1 d f DECF f,d Z dest ← f−1
0 0 0 1 0 0 d f IORWF f,d Z dest ← f | W, logical inclusive or
0 0 0 1 0 1 d f ANDWF f,d Z dest ← f & W, logical and
0 0 0 1 1 0 d f XORWF f,d Z dest ← f ^ W, logical exclusive or
0 0 0 1 1 1 d f ADDWF f,d C Z dest ← f+W
0 0 1 0 0 0 d f MOVF f,d Z dest ← f
0 0 1 0 0 1 d f COMF f,d Z dest ← ~f, bitwise complement
0 0 1 0 1 0 d f INCF f,d Z dest ← f+1
0 0 1 0 1 1 d f DECFSZ f,d dest ← f−1, then skip if zero
0 0 1 1 0 0 d f RRF f,d C dest ← CARRY<<7 | f>>1, rotate right through carry
0 0 1 1 0 1 d f RLF f,d C dest ← F<<1 | CARRY, rotate left through carry
0 0 1 1 1 0 d f SWAPF f,d dest ← f<<4 | f>>4, swap nibbles
0 0 1 1 1 1 d f INCFSZ f,d dest ← f+1, then skip if zero
0 1 op bit register Bit operations
0 1 0 0 bit f BCF f,b Clear bit b of f
0 1 0 1 bit f BSF f,b Set bit b of f
0 1 1 0 bit f BTFSC f,b Skip if bit b of f is clear
0 1 1 1 bit f BTFSS f,b Skip if bit b of f is set
1 0 op k Control transfers
1 0 0 0 k RETLW k Set W ← k, then return from subroutine
1 0 0 1 k CALL k Call subroutine, 8-bit address k
1 0 1 k GOTO k Jump to 9-bit address k[1]
1 1 op 8-bit immediate Operations with W and 8-bit literal: W ← OP(k,W)
1 1 0 0 k MOVLW k W ← k
1 1 0 1 k IORLW k Z W ← k | W, bitwise logical or
1 1 1 0 k ANDLW k Z W ← k & W, bitwise and
1 1 1 1 k XORLW k Z W ← k ^ W, bitwise exclusive or
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Mnemonic C
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Z
?
Description

*: Extended instruction, not available on most 12-bit PICs. Of the models with extended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using the high-order bits of the FSR. A few (e.g. PIC12F529T39A) have a separate bank select register which can be set with this instruction.
†: Extended instruction, only available on "enhanced baseline" PICs. Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.

ELAN Microelectronics clones (13 bit)

ELAN Microelectronics Corp. make a series of PICmicro-like microcontrollers with a 13-bit instruction word.[2] The instructions are mostly compatible with the mid-range 14-bit instruction set, but limited to a 6-bit register address (16 special-purpose registers and 48 bytes of RAM) and a 10-bit (1024 word) program space.

The 10-bit program counter is accessible as R2. Reads access only the low bits, and writes clear the high bits. An exception is the TBL instruction, which modifies the low byte while preserving bits 8 and 9.

The 7 accumulator-immediate instructions are renumbered relative to the 14-bit PICmicro, to fit into 3 opcode bits rather than 4, but they are all there, as well as an additional software interrupt instruction.

There are a few additional miscellaneous instructions, and there are some changes to the terminology (the PICmicro OPTION register is called the CONTrol register; the PICmicro TRIS registers 1–3 are called I/O control registers 5–7), but the equivalents are obvious.

13-bit EM78 instruction set[3]
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Mnemonic C
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Z
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Description
0 0 0 0 0 0 0 opcode Miscellaneous instructions
0 0 0 0 0 0 0 0 0 0 0 0 0 NOP* No operation (MOVW 0,W)
0 0 0 0 0 0 0 0 0 0 0 0 1 DAA C Decimal Adjust after Addition
0 0 0 0 0 0 0 0 0 0 0 1 0 CONTW* Write CONT register (CONT ← W)
0 0 0 0 0 0 0 0 0 0 0 1 1 SLEEP* Go into standby mode (WDT ← 0, stop clock)
0 0 0 0 0 0 0 0 0 0 1 0 0 CLRWDT* Restart watchdog timer (WDT ← 0)
0 0 0 0 0 0 0 0 0 f IOW f* Copy W to I/O control register (f = 5–7, 11–15)
0 0 0 0 0 0 0 0 1 0 0 0 0 ENI Enable interrupts
0 0 0 0 0 0 0 0 1 0 0 0 1 DISI Disable interrupts
0 0 0 0 0 0 0 0 1 0 0 1 0 RET Return from subroutine, W unmodified
0 0 0 0 0 0 0 0 1 0 0 1 1 RETI Return from interrupt; return & enable interrupts
0 0 0 0 0 0 0 0 1 0 1 0 0 CONTR Read CONT register (W ← CONT)
0 0 0 0 0 0 0 0 1 f IOR f Copy I/O control register to W (f = 5–7, 11–15)
0 0 0 0 0 0 0 1 0 0 0 0 0 TBL C Z PCL += W. preserve PC bits 8 & 9
0 0 opcode d register ALU operations same as 12- and 14-bit PIC
0 1 op bit register Bit operations same as 12- and 14-bit PIC
1 0 c k Control transfers same as 14-bit PIC
1 1 opcode 8-bit immediate Operations with W and 8-bit literal: W ← OP(k,W)
1 1 0 op k MOV/IOR/AND/XOR, same as 12-bit PIC
1 1 1 0 0 k RETLW k W ← k, then return from subroutine
1 1 1 0 1 k SUBLW k C Z W ← k−W (W ← k+~W+1)
1 1 1 1 0 k INT k Push PC, PC ← k (software interrupt, usually k=1)
1 1 1 1 1 k ADDLW k C Z W ← k+W
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Mnemonic C
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Description

*: Same opcode as 12-bit PIC
†: Instruction unique to EM78 instruction set with no PIC equivalent

Some models support multiple ROM or RAM banks, in a manner similar to other PIC microcontrollers.

Mid-range core devices (14 bit)

These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

14-bit PIC instruction set
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Mnemonic C
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Description
0 0 0 0 0 0 0 opcode Miscellaneous instructions
0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP No operation (MOVW 0,W)
0 0 0 0 0 0 0 0 0 0 1 0 0 0 RETURN Return from subroutine, W unmodified
0 0 0 0 0 0 0 0 0 0 1 0 0 1 RETFIE Return from interrupt
0 0 0 0 0 0 0 1 1 0 0 0 1 0 OPTION Copy W to OPTION register (deprecated)
0 0 0 0 0 0 0 1 1 0 0 0 1 1 SLEEP Go into standby mode
0 0 0 0 0 0 0 1 1 0 0 1 0 0 CLRWDT Restart watchdog timer
0 0 0 0 0 0 0 1 1 0 0 1 f TRIS f Copy W to tri-state register (f = 1, 2 or 3) (deprecated)
0 0 opcode d register ALU operations: dest ← OP(f,W)
0 0 0 0 0 0 1 f MOVWF f f ← W
0 0 0 0 0 1 d f CLR f,d Z dest ← 0, usually written CLRW or CLRF f
0 0 0 0 1 0 d f SUBWF f,d C Z dest ← f−W (dest ← f+~W+1)
0 0 0 0 1 1 d f DECF f,d Z dest ← f−1
0 0 0 1 0 0 d f IORWF f,d Z dest ← f | W, logical inclusive or
0 0 0 1 0 1 d f ANDWF f,d Z dest ← f & W, logical and
0 0 0 1 1 0 d f XORWF f,d Z dest ← f ^ W, logical exclusive or
0 0 0 1 1 1 d f ADDWF f,d C Z dest ← f+W
0 0 1 0 0 0 d f MOVF f,d Z dest ← f
0 0 1 0 0 1 d f COMF f,d Z dest ← ~f, bitwise complement
0 0 1 0 1 0 d f INCF f,d Z dest ← f+1
0 0 1 0 1 1 d f DECFSZ f,d dest ← f−1, then skip if zero
0 0 1 1 0 0 d f RRF f,d C dest ← CARRY<<7 | f>>1, rotate right through carry
0 0 1 1 0 1 d f RLF f,d C dest ← f<<1 | CARRY, rotate left through carry
0 0 1 1 1 0 d f SWAPF f,d dest ← f<<4 | f>>4, swap nibbles
0 0 1 1 1 1 d f INCFSZ f,d dest ← f+1, then skip if zero
0 1 op bit register Bit operations
0 1 0 0 bit f BCF f,b Clear bit b of f
0 1 0 1 bit f BSF f,b Set bit b of f
0 1 1 0 bit f BTFSC f,b Skip if bit b of f is clear
0 1 1 1 bit f BTFSS f,b Skip if bit b of f is set
1 0 c k Control transfers
1 0 0 k CALL k Call subroutine
1 0 1 k GOTO k Jump to address k
1 1 opcode 8-bit immediate Operations with W and 8-bit literal: W ← OP(k,W)
1 1 0 0 x x k MOVLW k W ← k
1 1 0 1 x x k RETLW k W ← k, then return from subroutine
1 1 1 0 0 0 k IORLW k Z W ← k | W, bitwise logical or
1 1 1 0 0 1 k ANDLW k Z W ← k & W, bitwise and
1 1 1 0 1 0 k XORLW k Z W ← k ^ W, bitwise exclusive or
1 1 1 0 1 1 k (reserved)
1 1 1 1 0 x k SUBLW k C Z W ← k−W (dest ← k+~W+1)
1 1 1 1 1 x k ADDLW k C Z W ← k+W
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Mnemonic C
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Z
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Description

Enhanced mid-range core devices (14 bit)

Enhanced mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and ‘C’ programming language optimizations. In particular. there are two INDF registers (INDF0 and INDF1), and two corresponding FSR register pairs (FSRnL and FSRnH). Special instructions use FSRn registers like address registers, with a variety of addressing modes.

14-bit enhanced PIC additional instructions
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Mnemonic C
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Description
0 0 0 0 0 0 0 opcode Miscellaneous instructions
0 0 0 0 0 0 0 0 0 0 0 0 0 1 RESET Software reset
0 0 0 0 0 0 0 0 0 0 1 0 1 0 CALLW Push PC, then jump to PCLATH:W
0 0 0 0 0 0 0 0 0 0 1 0 1 1 BRW PC ← PC + W, relative jump using W
0 0 0 0 0 0 0 0 0 1 0 n 0 0 MOVIW ++FSRn Z Increment FSRn, then W ← INDFn
0 0 0 0 0 0 0 0 0 1 0 n 0 1 MOVIW −−FSRn Z Decrement FSRn, then W ← INDFn
0 0 0 0 0 0 0 0 0 1 0 n 1 0 MOVIW FSRn++ Z W ← INDFn, then increment FSRn
0 0 0 0 0 0 0 0 0 1 0 n 1 1 MOVIW FSRn−− Z W ← INDFn, then decrement FSRn
0 0 0 0 0 0 0 0 0 1 1 n m MOVWI using FSRn INDFn ← W, same modes as MOVIW
0 0 0 0 0 0 0 0 1 k MOVLB k BSR ← k, move literal to bank select register
1 1 opcode d register ALU operations: dest ← OP(f,W)
1 1 0 1 0 1 d f LSLF f,d C Z dest ← f << 1, logical shift left
1 1 0 1 1 0 d f LSRF f,d C Z dest ← f >> 1, logical shift right
1 1 0 1 1 1 d f ASRF f,d C Z dest ← f >> 1, arithmetic shift right
1 1 1 0 1 1 d f SUBWFB f,d C Z dest ← f + ~W + C, subtract with carry
1 1 1 1 0 1 d f ADDWFC f,d C Z dest ← f + W + C, add with carry
1 1 opcode k Operations with literal k
1 1 0 0 0 1 0 n k ADDFSR FSRn,k FSRn ← FSRn + k, add 6-bit signed offset
1 1 0 0 0 1 1 k MOVLP k PCLATH ← k, move 7-bit literal to PC latch high
1 1 0 0 1 k BRA k PC ← PC + k, branch relative using 9-bit signed offset
1 1 1 1 1 1 0 n k MOVIW k[FSRn] Z W ← [FSRn+k], 6-bit signed offset
1 1 1 1 1 1 1 n k MOVWI k[FSRn] [FSRn+k] ← W, 6-bit signed offset
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Mnemonic C
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Z
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Description

PIC18 high end core devices (16 bit)

In 2000, Microchip introduced the PIC18 architecture.[2] Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.[4]

PIC18 16-bit instruction set[5]
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Mnemonic C
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Z
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N
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Description
0 0 0 0 0 0 0 opcode Miscellaneous instructions
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOP No operation
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 SLEEP Go into standby mode
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 CLRWDT Restart watchdog timer
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 PUSH Push PC on top of stack
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 POP Pop (and discard) top of stack
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 DAW C Decimal adjust W
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 TBLRD* Table read
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 TBLRD*+ Table read with postincrement
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 TBLRD*− Table read with postdecrement
0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 TBLRD+* Table read with pre-increment
0 0 0 0 0 0 0 0 0 0 0 0 1 1 mod TBLWR Table write, same modes as TBLRD
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 s RETFIE [, FAST] Return from interrupt
0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 s RETURN [, FAST] Return from subroutine
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RESET 0 0 0 Software reset
0 0 0 0 0 0 0 1 0 0 0 0 k MOVLB Move literal k to bank select register
0 0 0 0 1 opcode literal Literal operations: W ← OP(k,W)
0 0 0 0 1 0 0 0 k SUBLW k W ← k - W
0 0 0 0 1 0 0 1 k IORLW k W ← k | W, logical inclusive or
0 0 0 0 1 0 1 0 k XORLW k W ← k ^ W, exclusive or
0 0 0 0 1 0 1 1 k ANDLW k W ← k & W, logical and
0 0 0 0 1 1 0 0 k RETLW k RETURN W ← k
0 0 0 0 1 1 0 1 k MULLW k W ← k × W
0 0 0 0 1 1 1 0 k MOVLW k W ← k
0 0 0 0 1 1 1 1 k ADDLW k W ← k + W
0 opcode d a register ALU operations: dest ← OP(f,W)
0 0 0 0 0 0 1 a f MULWF f,a PRODH:PRODL ← W × f (unsigned)
0 0 0 0 0 1 d a f DECF f,d,a C Z N dest ← f − 1
0 0 0 1 0 0 d a f IORWF f,d,a Z N dest ← f | W, logical inclusive or
0 0 0 1 0 1 d a f ANDWF f,d,a Z N dest ← f & W, logical and
0 0 0 1 1 0 d a f XORWF f,d,a Z N dest ← f ^ W, exclusive or
0 0 0 1 1 1 d a f COMF f,d,a Z N dest ← ~f, bitwise complement
0 0 1 0 0 0 d a f ADDWFC f,d,a C Z N dest ← f + W + C
0 0 1 0 0 1 d a f ADDWF f,d,a C Z N dest ← f + W
0 0 0 0 1 0 d a f INCF f,d,a C Z N dest ← f + 1
0 0 1 0 1 1 d a f DECFSZ f,d,a dest ← f − 1, skip if 0
0 0 1 1 0 0 d a f RRCF f,d,a C Z N dest ← f>>1 | C<<7, rotate right through carry
0 0 1 1 0 1 d a f RLCF f,d,a C Z N dest ← f<<1 | C, rotate left through carry
0 0 1 1 1 0 d a f SWAPF f,d,a dest ← f<<4 | f>>4, swap nibbles
0 0 1 1 1 1 d a f INCFSZ f,d,a dest ← f + 1, skip if 0
0 1 0 0 0 0 d a f RRNCF f,d,a Z N dest ← f>>1 | f<<7, rotate right (no carry)
0 1 0 0 0 1 d a f RLNCF f,d,a Z N dest ← f<<1 | f>>7, rotate left (no carry)
0 1 0 0 1 0 d a f INFSNZ f,d,a dest ← f + 1, skip if not 0
0 1 0 0 1 1 d a f DCFSNZ f,d,a dest ← f − 1, skip if not 0
0 1 0 1 0 0 d a f MOVF f,d,a Z N dest ← f
0 1 0 1 0 1 d a f SUBFWB f,d,a C Z N dest ← W + ~f + C (dest ← W − f − C̅)
0 1 0 1 1 0 d a f SUBWFB f,d,a C Z N dest ← f + ~W + C (dest ← f − W − C̅)
0 1 0 1 1 1 d a f SUBWF f,d,a C Z N dest ← f − W (dest ← f + ~W + 1)
0 1 1 0 opcode a register ALU operations, do not write to W
0 1 1 0 0 0 0 a f CPFSLT f,a skip if f < W
0 1 1 0 0 0 1 a f CPFSEQ f,a skip if f == W
0 1 1 0 0 1 0 a f CPFSGT f,a skip if f > W
0 1 1 0 0 1 1 a f TSTFSZ f,a skip if f == 0
0 1 1 0 1 0 0 a f SETF f,a f ← 0xFF
0 1 1 0 1 0 1 a f CLRF f,a 1 f ← 0, PSR.Z ← 1
0 1 1 0 1 1 0 a f NEGF f,a C Z N f ← −f
0 1 1 0 1 1 1 a f MOVWF f,a f ← W
1 0 opc bit a register Bit operations
0 1 1 1 bit a f BTG f,b,a Toggle bit b of f
1 0 0 0 bit a f BSF f,b,a Set bit b of f
1 0 0 1 bit a f BCF f,b,a Clear bit b of f
1 0 1 0 bit a f BTFSS f,b,a Skip if bit b of f is set
1 0 1 1 bit a f BTFSC f,b,a Skip if bit b of f is clear
1 1 0 opc address Large-address operations
1 1 0 0 source MOVFF s,d Move absolute
1 1 1 1 destination
1 1 0 1 0 n BRA n Branch to PC + 2n
1 1 0 1 1 n RCALL n Subroutine call to PC + 2n
1 1 1 0 0 cond n Conditional branch
1 1 1 0 0 0 0 0 n BZ n Branch if PSR.Z is set
1 1 1 0 0 0 0 1 n BNZ n Branch if PSR.Z is clear
1 1 1 0 0 0 1 0 n BC n Branch if PSR.C is set
1 1 1 0 0 0 1 1 n BNC n Branch if PSR.C is clear
1 1 1 0 0 1 0 0 n BOV n Branch if PSR.V is set
1 1 1 0 0 1 0 1 n BNOV n Branch if PSR.V is clear
1 1 1 0 0 1 1 0 n BN n Branch if PSR.N is set
1 1 1 0 0 1 1 1 n BNN n Branch if PSR.N is clear
1 1 1 0 1 0 (reserved)
1 1 1 0 1 1 opc k 2-word instructions
1 1 1 0 1 1 0 s k (lsbits) CALL k[, FAST] Call subroutine
1 1 1 1 k (msbits)
1 1 1 0 1 1 1 0 0 0 f k (msb) LFSR f,k Move 12-bit literal to FSRf
1 1 1 1 0 0 0 0 k (lsbits)
1 1 1 0 1 1 1 1 k (lsbits) GOTO k Absolute jump, PC ← k
1 1 1 1 k (msbits)
1 1 1 1 k (No operation)
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Mnemonic C
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N
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Description

PIC24 and dsPIC 16-bit microcontrollers

In 2001, Microchip introduced the dsPIC series of chips,[6] which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.

Instructions come in 2 main varieties. One is like the classic PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result. The W registers are memory-mapped. so the f operand may be any W register,

The other form, new to the PIC24, specifies 3 W register operands, 2 of which allow a 3-bit addressing mode specification:

PIC24 addressing modes
s operand d operand Description
ppp Reg Syntax qqq Reg Syntax
000 ssss Ws 000 dddd Wd Register direct
001 ssss [Ws] 001 dddd [Wd] Indirect
010 ssss [Ws−−] 010 dddd [Wd−−] Indirect with postdecrement
011 ssss [Ws++] 011 dddd [Wd++] Indirect with postincrement
100 ssss [−−Ws] 100 dddd [−−Wd] Indirect with predecrement
101 ssss [++Ws] 101 dddd [++Wd] Indirect with preincrement
11x ssss [Ws+Ww] 11x dddd [Wd+Ww] Indirect with register offset
11k kkkk #u5 (Unused, illegal) 5-bit unsigned immediate

The register offset addressing mode is only available to 2-operand instructions. 3-operand instructions use Ww as the second source operand, and use this encoding for an unsigned 5-bit immediate source. Note that the same Ww may be added to both Wd and Ws.

A few instructions are 2 words long. The second word is a NOP, which includes up to 16 bits of additional immediate operand.

PIC24 24-bit instruction set[7]
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Mnemonic C
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Description
0 0 0 0 opcode offset Control transfers
0 0 0 0 0 0 0 0 NOP No operation (& 2nd instruction word)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n NOP Second word of absolute branch (bits 22:16)
0 0 0 0 0 0 0 0 n NOP Second word of DO instruction
0 0 0 0 0 0 0 1 0 op —0— a Computed control transfer (to 16-bit Wa)
0 0 0 0 0 0 0 1 0 0 0 —0— a CALL Ra Push PC, jump to Wa
0 0 0 0 0 0 0 1 0 0 1 —0— a RCALL Ra Push PC, jump to PC+2×Wa
0 0 0 0 0 0 0 1 0 1 0 —0— a GOTO Ra Jump to Wa
0 0 0 0 0 0 0 1 0 1 1 —0— a BRA Ra Jump to PC+2×Wa
0 0 0 0 0 0 1 0 n<15:1> 0 CALL addr23 Push PC, jump to absolute address
—0— 0 0 0 0 0 0 0 0 0 n<22:16>
0 0 0 0 0 0 1 1 (Reserved)
0 0 0 0 0 1 0 0 n 0 GOTO addr23 Jump to absolute address
—0— 0 0 0 0 0 0 0 0 0 n<22:16>
0 0 0 0 0 1 0 1 0 B k d RETLW #k,Wd Wn[.B] = #u10, pop PC
0 0 0 0 0 1 1 0 0 0 —0— RETURN pop PC
0 0 0 0 0 1 1 0 0 1 —0— RETFIE C Z N pop SR, PC
0 0 0 0 0 1 1 1 n RCALL address Push PC, PC += 2*s16
0 0 0 0 1 0 0 0 0 0 k DO #k, addr Zero-overhead loop; k+1 is repeat count, PC+2n last instruction
—0— n
0 0 0 0 1 0 0 0 0 0 k REPEAT #k Repeat next instruction k+1 times
0 0 0 0 1 0 0 0 n RCALL address Push PC, PC += 2*s16
0 0 0 0 1 0 1 (Reserved)
0 0 0 0 1 1 0 a n BRA Oa, addr If accumulator an overflowed, PC += 2*simm16
0 0 0 0 1 1 1 a n BRA Sa, addr If accumulator a saturated, PC += 2*simm16
0 opcode w B q d p s ALU operations: Wd ← OP(Ww,Ws)
0 0 0 1 0 w B q d p s SUBR[.B] Ww,Ws,Wd C Z N Wd ← Ws − Ww (Wd ← Ws + ~Ww + 1)
0 0 0 1 1 w B q d p s SUBBR[.B] Ww,Ws,Wd C Z N Wd ← Ws + ~Ww + C (Wd ← Ws − Ww − C̅)
0 0 1 0 k d MOV #k,Wd Wd ← #imm16
0 0 1 1 cond n Conditional branch to PC+2*n
0 0 1 1 0 0 0 0 n BRA OV,addr Branch if PSR.V is set
0 0 1 1 0 0 0 1 n BRA C,addr Branch if PSR.C is set
0 0 1 1 0 0 1 0 n BRA Z,addr Branch if PSR.Z is set
0 0 1 1 0 0 1 1 n BRA N,addr Branch if PSR.N is set
0 0 1 1 0 1 0 0 n BRA LE,addr Branch if PSR.Z, or PSR.N ≠ PSR.V
0 0 1 1 0 1 0 1 n BRA LT,addr Branch if PSR.N ≠ PSR.V
0 0 1 1 0 1 1 0 n BRA LEU,addr Branch if PSR.Z is set, or PSR.C is clear
0 0 1 1 0 1 1 1 n BRA addr Branch unconditionally
0 0 1 1 1 0 0 0 n BRA NOV,addr Branch if PSR.V is clear
0 0 1 1 1 0 0 1 n BRA NC,addr Branch if PSR.C is clear
0 0 1 1 1 0 1 0 n BRA NZ,addr Branch if PSR.Z is clear
0 0 1 1 1 0 1 1 n BRA NN,addr Branch if PSR.N is clear
0 0 1 1 1 1 0 0 n BRA GT,addr Branch if PSR.Z is clear, and PSR.N = PSR.V
0 0 1 1 1 1 0 1 n BRA GE,addr Branch if PSR.N = PSR.V
0 0 1 1 1 1 1 0 n BRA GTU,addr Branch if PSR.Z is clear, and PSR.C is set
0 0 1 1 1 1 1 1 n (Reserved)
0 opcode w B q d p s ALU operations: Wd ← OP(Ww,Ws)
0 1 0 0 0 w B q d p s ADD[.B] Ww,Ws,Wd C Z N Wd ← Ww + Ws
0 1 0 0 1 w B q d p s ADDC[.B] Ww,Ws,Wd C Z N Wd ← Ww + Ws + C
0 1 0 1 0 w B q d p s SUB[.B] Ww,Ws,Wd C Z N Wd ← Ww − Ws
0 1 0 1 1 w B q d p s SUBB[.B] Ww,Ws,Wd C Z N Wd ← Ww + ~Ws + C (Wd ← Ww − ~Ws − C̅)
0 1 1 0 0 w B q d p s AND[.B] Ww,Ws,Wd Z N Wd ← Ww & Ws, logical and
0 1 1 0 1 w B q d p s XOR[.B] Ww,Ws,Wd Z N Wd ← Ww ^ Ws, exclusive or
0 1 1 1 0 w B q d p s IOR[.B] Ww,Ws,Wd Z N Wd ← Ww | Ws, inclusive or
0 1 1 1 1 w B q d p s MOV[.B] Ws,Wd Z N Wd ← Ws (offset mode allowed)
1 0 0 0 0 f d MOV f,Wd Wd ← f
1 0 0 0 1 f s MOV Ws,f f ← Ws
1 0 0 1 0 k B k d k s MOV [Ws+s10],Wd Load with 10-bit signed offset
1 0 0 1 1 k B k d k s MOV Ws,[Wd+s10] Store with 10-bit signed offset
1 0 1 0 0 opc b Z B 0 0 0 p s Bit operations on Ws
1 0 1 0 0 0 0 0 b 0 B 0 0 0 p s BSET[.B] #b,Ws Set bit b of Ws
1 0 1 0 0 0 0 1 b 0 B 0 0 0 p s BCLR[.B] #b,Ws Clear bit b of Ws
1 0 1 0 0 0 1 0 b 0 B 0 0 0 p s BTG[.B] #b,Ws Toggle bit b of Ws
1 0 1 0 0 0 1 1 b 0 0 0 0 0 p s BTST.C #b,Ws C Set PSR.C = bit b of Ws
1 0 1 0 0 0 1 1 b 1 0 0 0 0 p s BTST.Z #b,Ws Z Set PSR.Z to complement of bit b of Ws
1 0 1 0 0 1 0 0 b Z 0 0 0 0 p s BTSTS.z #b,Ws C/Z Bit test (into C or Z), then set
1 0 1 0 0 1 0 1 Z w 0 0 0 0 p s BTST.z Ww,Ws C/Z Test bit (dynamic)
1 0 1 0 0 1 1 0 b 0 0 0 0 0 p s BTSS #b,Ws Test bit b of Ws, skip if set
1 0 1 0 0 1 1 1 b 0 0 0 0 0 p s BTSS #b,Ws Test bit b of Ws, skip if clear
1 0 1 0 1 opc b f Bit operations on f
1 0 1 0 1 0 0 0 b f b BSET[.B] f, #b Set bit b of f
1 0 1 0 1 0 0 1 b f BCLR.B #b,f Clear bit b of f
1 0 1 0 1 0 1 0 b f BTG.B #b,f Toggle bit b of f
1 0 1 0 1 0 1 1 b f BTST.B #b,f Z Test bit b of f
1 0 1 0 1 1 0 0 b f BTSTS.B #b,f Z Test bit b of f, then set
1 0 1 0 1 1 0 1 Z w 0 0 0 0 p s BSW.z Ws,Ww Copy PSW bit to bit Ww of Wb
1 0 1 0 1 1 1 0 b f BTSS #b,f Test bit b of f, skip if set
1 0 1 0 1 1 1 1 b f BTSC #b,f Test bit b of f, skip if clear
1 0 1 1 0 0 opc B k d Register-immediate operations
1 0 1 1 0 0 0 0 0 B k d ADD[.B] #u10,Wd C N Z Wd ← Wd + imm10
1 0 1 1 0 0 0 0 1 B k d ADC[.B] #u10,Wd C N Z Wd ← Wd + imm10 + C
1 0 1 1 0 0 0 1 0 B k d SUB[.B] #u10,Wd C N Z Wd ← Wd − imm10
1 0 1 1 0 0 0 1 1 B k d SUBB[.B] #u10,Wd C N Z Wd ← Wd − imm10 − C̅
1 0 1 1 0 0 1 0 0 B k d AND[.B] #u10,Wd N Z Wd ← Wd & imm10
1 0 1 1 0 0 1 0 1 B k d XOR[.B] #u10,Wd N Z Wd ← Wd ^ imm10
1 0 1 1 0 0 1 1 0 B k d IOR[.B] #u10,Wd N Z Wd ← Wd | imm10
1 0 1 1 0 0 1 1 1 B k d MOV[.B] #u10,Wd Wd ← imm10
1 0 1 1 0 1 opc B D f ALU operations: dest ← OP(f,W0)
1 0 1 1 0 1 0 0 0 B D f ADD[.B] f[,WREG] C N Z dest ← f + W0
1 0 1 1 0 1 0 0 1 B D f ADC[.B] f[,WREG] C N Z dest ← f + W0 + C
1 0 1 1 0 1 0 1 0 B D f SUB[.B] f[,WREG] C N Z dest ← f − W0
1 0 1 1 0 1 0 1 1 B D f SUBB[.B] f[,WREG] C N Z dest ← f − W0 + C̅
1 0 1 1 0 1 1 0 0 B D f AND[.B] f[,WREG] N Z dest ← f & W0
1 0 1 1 0 1 1 0 1 B D f XOR[.B] f[,WREG] N Z dest ← f ^ W0
1 0 1 1 0 1 1 1 0 B D f IOR[.B] f[,WREG] N Z dest ← f | W0
1 0 1 1 0 1 1 1 1 B 1 f MOV[.B] WREG,f dest ← W0
1 0 1 1 1 0 0 op w d 0 p s 16×16→32 multiplication
1 0 1 1 1 0 0 0 0 w d 0 p s MUL.UU Ww,Ws,Wd Wd+1:Wd ← Wb * Ws (unsigned)
1 0 1 1 1 0 0 0 1 w d 0 p s MUL.US Ww,Ws,Wd Wd+1:Wd ← Wb * Ws (Ws signed)
1 0 1 1 1 0 0 1 0 w d 0 p s MUL.SU Ww,Ws,Wd Wd+1:Wd ← Wb * Ws (Wb signed)
1 0 1 1 1 0 0 1 1 w d 0 p s MUL.SS Ww,Ws,Wd Wd+1:Wd ← Wb * Ws (signed)
1 0 1 1 1 0 1 op w d p s Program memory access
1 0 1 1 1 0 1 0 0 B qqq d p s TBLRDL [Ws],Wd Wd ← PROGRAM[TBLPAG:Ws] (bits 15:0)
1 0 1 1 1 0 1 0 1 B qqq d p s TBLRDH [Ws],Wd Wd ← PROGRAM[TBLPAG:Ws] (bit 23:16)
1 0 1 1 1 0 1 1 0 B qqq d p s TBLWTL Ws,[Wd] PROGRAM[TBLPAG:Wd] ← Ws (bits 15:0)
1 0 1 1 1 0 1 1 1 B qqq d p s TBLWTH Ws,[Wd] PROGRAM[TBLPAG:Wd] ← Ws (bit 23:16)
1 0 1 1 1 1 0 0 0 B 0 f MUL[.B] f W3:W2 ← f * W0 (unsigned)
1 0 1 1 1 1 0 1 (Reserved)
1 0 1 1 1 1 1 0 0 0 000 d 0 p s MOV.D Ws,Wd Move register pair (source may be memory)
1 0 1 1 1 1 1 0 1 0 q d 000 s 0 MOV.D Ws,Wd Move register pair (dest may be memory)
1 0 1 1 1 1 1 1 (Reserved)
1 1 0 0 0 m A S x y i j a DSP MAC (dsPIC only)
1 1 0 0 1 Other DSP instructions (dsPIC only)
1 1 0 0 1 1 1 1 0 0 000 d p s FF1R Ws,Wd Find first one from right (lsb)
1 1 0 0 1 1 1 1 1 0 000 d p s FF1L Ws,Wd Find first one from left (msb)
1 1 0 1 0 0 opc B q d p s Shift/rotate W register
1 1 0 1 0 0 0 0 0 B q d p s SL[.B] Ws,Wd C N Z Wd ← Ws << 1, shift left (into carry)
1 1 0 1 0 0 0 1 0 B q d p s LSR[.B] Ws,Wd C N Z Wd ← Ws >> 1, logical shift right
1 1 0 1 0 0 0 1 1 B q d p s ASR[.B] Ws,Wd C N Z Wd ← Ws >> 1, arithmetic shift right
1 1 0 1 0 0 1 0 0 B q d p s RLNC[.B] Ws,Wd N Z Wd ← Ws <<< 1, rotate left (no carry)
1 1 0 1 0 0 1 0 1 B q d p s RLC[.B] Ws,Wd C N Z C:Wd ← Ws:C << 1, rotate left through carry
1 1 0 1 0 0 1 1 0 B q d p s RRNC[.B] Ws,Wd N Z Wd ← Ws >>> 1, rotate right (no carry)
1 1 0 1 0 0 1 1 1 B q d p s RRC[.B] Ws,Wd C N Z Wd:C ← C:Ws >> 1, rotate right through carry
1 1 0 1 0 1 opc B D f Shift/rotate f
1 1 0 1 0 1 0 0 0 B D f SL[.B] f[,WREG] C N Z dest ← f << 1, shift left (into carry)
1 1 0 1 0 1 0 1 0 B D f LSR[.B] f[,WREG] C N Z dest ← f >> 1, logical shift right
1 1 0 1 0 1 0 1 1 B D f ASR[.B] f[,WREG] C N Z dest ← f >> 1, arithmetic shift right
1 1 0 1 0 1 1 0 0 B D f RLNC[.B] f[,WREG] N Z dest ← f <<< 1, rotate left (no carry)
1 1 0 1 0 1 1 0 1 B D f RLC[.B] f[,WREG] C N Z C:dest ← f:C << 1, rotate left through carry
1 1 0 1 0 1 1 1 0 B D f RRNC[.B] f[,WREG] N Z dest ← f >>> 1, rotate right (no carry)
1 1 0 1 0 1 1 1 1 B D f RRC[.B] f[,WREG] C N Z dest:C ← C:f >> 1, rotate right through carry
1 1 0 1 1 0 0 0 U t v W 0 0 s 32/16 and 16/16 divide steps (prefix with REPEAT #17)
1 1 0 1 1 0 0 0 0 0000 v 0 0 0 s DIV.S Wv,Ws C N Z Divide step, W0 ← Wv/Ws, W1 ← remainder
1 1 0 1 1 0 0 0 0 t v 1 0 0 s DIV.SD Wv,Ws C N Z Divide step, W0 ← Wt:Wv/Ws, W1 ← remainder
1 1 0 1 1 0 0 0 1 0000 v 0 0 0 s DIV.U Wv,Ws C N Z Divide step, W0 ← Wv/Ws, W1 ← remainder
1 1 0 1 1 0 0 0 1 t v 1 0 0 s DIV.UD Wv,Ws C N Z Divide step, W0 ← Wt:Wv/Ws, W1 ← remainder
1 1 0 1 1 0 0 1 0 t 0 0 0 0 0 0 0 s DIVF Wt,Ws C N Z Divide step, W0 ← Wt:0/Ws, W1 ← remainder
1 1 0 1 1 0 1 (Reserved)
1 1 0 1 1 1 0 0 (Reserved)
1 1 0 1 1 1 0 0 0 w d 0 0 0 s SL Ww,Ws,Wd N Z Wd ← Wv << Ws
1 1 0 1 1 1 0 0 0 w d 1 0 0 k SL Ww,#u4,Wd N Z Wd ← Wv << imm4
1 1 0 1 1 1 1 0 0 w d 0 0 0 s LSR Ww,Ws,Wd N Z Wd ← Wv>> Ws, logical shift right
1 1 0 1 1 1 1 0 0 w d 1 0 0 k LSR Ww,#u4,Wd N Z Wd ← Wv>> imm4, logical shift right
1 1 0 1 1 1 1 0 1 w d 0 0 0 s ASR Ww,Ws,Wd N Z Wd ← Wv>> Ws, arithmetic shift right
1 1 0 1 1 1 1 0 1 w d 1 0 0 k ASR Wv,#u4,Wd N Z Wd ← Wv>> imm4, arithmetic shift right
1 1 0 1 1 1 1 1 0 0000 d p s FBCL Ws,Wd C Find permissible arithmetic normalization shift
1 1 1 0 0 0 0 0 0 0000 B 0 0 0 p s CP0[.B] Ws C N Z Compare with zero, Ws − 0
1 1 1 0 0 0 0 1 0 w B 0 0 0 p s CP[.B] Ww,Ws C N Z Compare, Wb − Ws (Wb + ~Ws + 1)
1 1 1 0 0 0 0 1 1 w B 0 0 0 p s CPB[.B] Ww,Ws C N Z Compare with borrow, Wb + ~Ws + C (Wb − Ws − C̅)
1 1 1 0 0 0 1 0 0 B 0 f CP0[.B] Ws C N Z Compare with zero, f − 0
1 1 1 0 0 0 1 1 0 B 0 f CP[.B] f C N Z Compare f, f − W0
1 1 1 0 0 0 1 1 1 B 0 f CPB[.B] f C N Z Compare f with borrow, f + ~W0 + C (f − W0 − C̅)
1 1 1 0 0 1 0 (Reserved)
1 1 1 0 0 1 1 0 0 w B 0 0 0 0 0 0 s CPSGT[.B] Ww,Ws Compare and skip if greater than (Wb > Ws, signed)
1 1 1 0 0 1 1 0 1 w B 0 0 0 0 0 0 s CPSLT[.B] Ww,Ws Compare and skip if less than (Wb < Ws, signed)
1 1 1 0 0 1 1 1 0 w B 0 0 0 0 0 0 s CPSNE[.B] Ww,Ws Compare and skip if not equal (Wb ≠ Ws)
1 1 1 0 0 1 1 1 1 w B 0 0 0 0 0 0 s CPSNE[.B] Ww,Ws Compare and skip if equal (Wb = Ws)
1 1 1 0 1 0 0 0 0 B q d p s INC[.B] Ws,Wd C N Z Wd ← Ws+1
1 1 1 0 1 0 0 0 1 B q d p s INC2[.B] Ws,Wd C N Z Wd ← Ws+2
1 1 1 0 1 0 0 1 0 B q d p s DEC[.B] Ws,Wd C N Z Wd ← Ws−1
1 1 1 0 1 0 0 1 1 B q d p s DEC2[.B] Ws,Wd C N Z Wd ← Ws−2
1 1 1 0 1 0 1 0 0 B q d p s NEG[.B] Ws,Wd C N Z Wd ← ~Ws+1
1 1 1 0 1 0 1 0 1 B q d p s COM[.B] Ws,Wd N Z Wd ← ~Ws
1 1 1 0 1 0 1 1 0 B q d 000 0000 CLR[.B] Wd Wd ← 0
1 1 1 0 1 0 1 1 1 B q d 000 0000 SETM[.B] Wd Wd ← ~0
1 1 1 0 1 1 0 0 0 B D f INC[.B] f[,WREG] C N Z dest ← f+1
1 1 1 0 1 1 0 0 1 B D f INC2[.B] f[,WREG] C N Z dest ← f+2
1 1 1 0 1 1 0 1 0 B D f DEC[.B] f[,WREG] C N Z dest ← f−1
1 1 1 0 1 1 0 1 1 B D f DEC[.B] f[,WREG] C N Z dest ← f−2
1 1 1 0 1 1 1 0 0 B D f NEG[.B] f[,WREG] C N Z dest ← ~f+1
1 1 1 0 1 1 1 0 1 B D f COM[.B] f[,WREG] N Z dest ← ~f
1 1 1 0 1 1 1 1 0 B D f CLR[.B] f[,WREG] dest ← 0
1 1 1 0 1 1 1 1 1 B D f SETM[.B] f[,WREG] dest ← ~0
1 1 1 1 0 0 m A 1 x y i j opc DSP MPY/MAC/ED/EDAC (dsPIC only)
1 1 1 1 0 1 (Reserved)
1 1 1 1 1 0 0 0 f 0 PUSH f Push f on top of stack
1 1 1 1 1 0 0 1 f 0 POP f Pop f from top of stack
1 1 1 1 1 0 1 0 0 0 k LNK #u14 Push W14, W14 ← W15, W15 += u14
1 1 1 1 1 0 1 0 1 0 —0— ULNK W15 ← W14, pop W14
1 1 1 1 1 0 1 1 0 0 000 d p s SE Ws,Wd C N Z Wd ← sign_extend(Ws), copy bit 7 to bits 15:8
1 1 1 1 1 0 1 1 1 0 000 d p s ZE Ws,Wd 1 0 Z Wd ← zero_extend(Ws), clear bits 15:8
1 1 1 1 1 1 0 0 0 0 k DISI #u14 Disable interrupt for k+1 cycles
1 1 1 1 1 1 0 1 0 0 000 d 000 s EXCH Ws,Wd Swap contents of registers Ws, Wd
1 1 1 1 1 1 0 1 0 1 000 0000 000 s DAW.B Ws C Decimal adjust based on C, DC
1 1 1 1 1 1 0 1 1 B 000 0000 000 s SWAP[.B] Ws Swap halves of Ws
1 1 1 1 1 1 1 0 0 0 —0— RESET Software reset
1 1 1 1 1 1 1 0 0 1 0 —0— k PWRSAV #u1 Go into sleep or idle mode
1 1 1 1 1 1 1 0 0 1 1 —0— CLRWDT Clear watchdog timer
1 1 1 1 1 1 1 0 1 0 0 —0— POP.S Pop shadow registers (W0–3, part of PSR)
1 1 1 1 1 1 1 0 1 0 1 —0— PUSH.S Push shadow registers (W0–3, part of PSR)
1 1 1 1 1 1 1 0 1 1 (Reserved)
1 1 1 1 1 1 1 1 NOPR No operation (version #2)

References

  1. PIC10F200/202/204/206 Data Sheet (PDF). Microchip Technology. 2007. p. 52.<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
  2. http://www.emc.com.tw/eng/products.asp
  3. ELAN Microelectronics Corp. (September 2005), EM78P157N 8-bit microcontroller with OTP ROM Product Specification (PDF), retrieved 2012-04-02<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
  4. http://www.microchipc.com/sourcecode/
  5. Microchip Technology, Inc. (2007), PIC18F1220/1320 Data Sheet (PDF), retrieved 2012-04-02<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>
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  7. dsPIC30F Programmer's Reference Manual (PDF), Microchip Technology, 2008, DS70157C, retrieved 2012-07-02<templatestyles src="Module:Citation/CS1/styles.css"></templatestyles>