Soft microprocessor

From Infogalactic: the planetary knowledge core
Jump to: navigation, search

A soft microprocessor (also called softcore microprocessor or a soft processor) is a microprocessor core that can be wholly implemented using logic synthesis. It can be implemented via different semiconductor devices containing programmable logic (e.g., ASIC, FPGA, CPLD), including both high-end and commodity variations.[1]

Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.[2] In those multi-core systems, rarely used resources can be shared between all the cores in a cluster, leading to Jan's Razor.

Jan's Razor: In a chip multiprocessor design, strive to leave out all but the minimal kernel set of features from each processing element, so as to maximize processing elements per die.[3]

— Jan Gray

While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a multi-core processor. The number of soft processors on a single FPGA is only limited by the size of the FPGA.[4] Some people have put dozens or hundreds of soft microprocessors on a single FPGA.[5][6][7][8][9]

Core comparison

Processor Developer Open Source Bus Support Notes Project Home Description Language
TSK3000A Altium No Royalty-Free Wishbone 32-bit R3000 style RISC Modified Harvard Architecture CPU Embedded Design on Altium Wiki
TSK51/52 Altium No Royalty-Free Wishbone / Intel 8051 8-bit Intel 8051 instruction set compatible, lower clock cycle alternative Embedded Design on Altium Wiki
OpenSPARC T1 Sun Yes 64-bit Verilog
MicroBlaze Xilinx No PLB, OPB, FSL, LMB, AXI4 Xilinx MicroBlaze
PicoBlaze Xilinx Yes Xilinx PicoBlaze VHDL, Verilog
Nios, Nios II Altera No Avalon Altera Nios II Verilog
Cortex-M1 ARM No [6] 70-200 MHz, 32bit RISC [7] Verilog
eSi-RISC EnSilica No AMBA AXI, AHB and APB Configurable as 16 or 32-bit. Supports ASIC and FPGA. EnSilica eSi-RISC Verilog
LatticeMico32 Lattice Yes Wishbone LatticeMico32 Verilog
LEON3/4 Aeroflex Gaisler Yes AMBA2 SPARC V8 Aeroflex Gaisler VHDL
Navré Sébastien Bourdeauducq Yes Direct SRAM Atmel AVR compatible 8-bit RISC Project page at Opencores Verilog
OpenRISC OpenCores Yes Wishbone 32-bit; Done in ASIC, Actel, Altera, Xilinx FPGA OR1K Verilog
ARC ARC International, Synopsys No 16/32-bit ISA RISC DesignWare ARC Verilog
pAVR Doru Cuturela Yes Atmel AVR compatible 8-bit RISC Project page at Opencores VHDL
AEMB Shawn Tan Yes Wishbone MicroBlaze EDK 3.2 compatible AEMB Verilog
OpenFire Virginia Tech CCM Lab Yes OPB, FSL Binary compatible with the MicroBlaze [8] [10] Verilog
SecretBlaze LIRMM, University of Montpellier / CNRS Yes Wishbone MicroBlaze ISA, VHDL SecretBlaze VHDL
RISC-V UC Berkeley Yes RISC-V ISA, Xilinx Zynq Chisel
SYNPIC12 Miguel Angel Ajo Pelayo Yes MIT PIC12F compatible, program synthesised in gates VHDL
PacoBlaze Pablo Bleyer Yes Compatible with the PicoBlaze processors PacoBlaze Verilog
CPU86 HT-Lab Yes 8088 compatible CPU in VHDL cpu86 VHDL
xr16 Jan Gray No XSOC abstract bus 16-bit RISC CPU + SoC featured in Circuit Cellar Magazine #116-118 XSOC/xr16 Schematic
JOP Martin Schoeberl Yes SimpCon / Wishbone (extension) Stack oriented, hard real-time support, executes Java bytecode directly Jop VHDL
ERIC5 Entner Electronics No 9-bit RISC, very small size, C-programmable ERIC5 VHDL
YASEP Yann Guidon Yes AGPLv3 Direct SRAM 16 or 32 bits, RTL in VHDL & asm in JS, microcontroller subset : ready (Firefox required) VHDL
Zet Zeus Gómez Marmolejo Yes Wishbone x86 PC clone Zet Verilog
ZPU Zylin AS Yes Wishbone Stack based CPU, configurable 16/32 bit datapath, eCos support Zylin CPU VHDL
ZPUino Álvaro Lopes Yes Wishbone Zylin's ZPU based SoC, 32 bit, Linux support. ZPUino VHDL

See also


  1. "Zet soft core running Windows 3.0" by Andrew Felch 2011
  2. "FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006
  3. "Multiprocessors, Jan's Razor, resource sharing, and all that" by Jan Gray 2002
  4. MicroBlaze Soft Processor: Frequently Asked Questions
  5. István Vassányi. "Implementing processor arrays on FPGAs". 1998. [1]
  6. Zhoukun WANG and Omar HAMMAMI. "A 24 Processors System on Chip FPGA Design with Network on Chip". [2]
  7. John Kent. "Micro16 Array - A Simple CPU Array" [3]
  8. Kit Eaton. "1,000 Core CPU Achieved: Your Future Desktop Will Be a Supercomputer". 2011. [4]
  9. "Scientists Squeeze Over 1,000 Cores onto One Chip". 2011. [5]

External links