SpecC

SpecC is a System Description Language (SDL), or System-level Design Language (SLDL), and is an extension of the ANSI C programming language. It is used to aid the design and specification of digital embedded systems, providing improved productivity whilst retaining the ability to change a design at functional and specification level, unlike HDLs like Verilog and VHDL. An architectural model can be created which allows other tools to directly map the design onto silicon or FPGA. The main aim is for the reuse, exchange and integration of IP at various levels of abstraction.

The language and design methodology were created by Rainer Dömer and Daniel Gajski at the Centre for Embedded Computer Systems at University of California, Irvine in 2001.

Similar projects and design methodologies include SystemC, an SDL based on C++. Although this rival language has seen much more widespread industry usage (although SpecC is popular in Japan), SpecC retains simplicity whilst also providing the vital features of any SDL, such as concurrency (SpecC provides pipelined and parallel flows), synchronisation, state transitions (not available in Verilog), and composite data types.

See also

• Accellera
• SystemC
• SystemVerilog

External links

• SpecC information
• Technical Report, 2006 (PDF)