Cannonlake
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| Created | H2 2017[1] |
|---|---|
| Transistors | 10 nm transistors |
| Architecture | x86 |
| Instructions | MMX, AES-NI, CLMUL, FMA3 |
| Extensions | |
| Socket | LGA 1151 |
| Predecessor | Kaby Lake (Optimization)[2] |
| Successor | |
| Brand name(s) |
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Cannonlake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Skylake microarchitecture, expected to be released in the second half of 2017.[1][3] As a die shrink, Cannonlake is a new process in Intel's "Process-Architecture-Optimization" execution plan as the next step in semiconductor fabrication.[4] Cannonlake will be used in conjunction with Intel 200 Series chipsets, also known as Union Point. The platform as a whole will be named Union Bay.[4]
It has been speculated for a long time that reaching smaller process nodes would become impractical, leading to the end of Moore's Law. Intel however believes that it will be possible to reach at least 7 nm, though it will perhaps require use of materials other than silicon,[5] such as indium gallium arsenide (InGaAs).
The successors of the Cannonlake microarchitecture will be Icelake and Tigerlake, which will represent Architecture and Optimization of the Intel Process-Architecture-Optimization Model.[6][7]
Features
- 200 Series chipset (Union Point)
- Thermal design power (TDP) up to 95 W (LGA 1151)
See also
References
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